A significant problem faced by mobile, e.g., battery powered computers is the length of time such computers are capable of operating between charges. An additional concern is heat dissipation of the electronics. As computer processors become more capable, they tend to run at higher clock rates and to dissipate more power. In addition, more capable peripherals, e.g., higher capacity hard drives and wireless high speed networks, also compete with the main computer processor for an ever-increasing portion of the available battery power. At the same time, the size and weight of portable computers is constantly being reduced to make them more portable. Since batteries generally are a very significant component of the weight of portable computers and other portable devices, the tendency has been to maintain battery size and thus battery capacity at a minimum. The compact nature of portable devices also intensifies heat dissipation issues.
A great deal of time, expense and effort has been directed to techniques for extending the operating life of portable computers. Presently, typical processors and computer systems include circuitry and software for disabling various power-draining functions of portable computers when those functions are unused for some extensive period. For example, various techniques have been devised for turning off the display screen when it has not been used for some selected period. Similar processes measure the length of time between use of hard drives and disable rotation after some period. Another of these processes is adapted to put a central processor into a quiescent condition after a period of inactivity.
In general, these processes are useful in extending the operating life of a portable computer. However, the life still does not in general achieve a desirable duration. In fact, battery life is a highly competitive specification among portable processor and computer manufacturers, and there is an almost universal desire for more battery life.
There has been a significant amount of research conducted from which processors requiring less power might be produced. Most processors used in computer systems today are made using complimentary metal oxide semiconductor (CMOS) technology. The power consumed by a CMOS integrated circuit is comprised of two components, a static portion and a dynamic portion. Dynamic power is given approximately by p=CV2f, where C is the active switching capacitance, V is the supply voltage, and f is the frequency of operation, and static power is expressed as idle or “off” current times voltage.
It is desirable to operate a processor at the lowest possible voltage at a frequency that provides the computing resource desired by the user at any given moment. For instance, if a processor is operating at 600 MHz, and the user runs a process that is only half as demanding of the processor, the frequency can be decreased by approximately a factor of two. Correspondingly, in many cases the voltage can also be decreased by a factor of two. Therefore, dynamic power consumption can be reduced by a factor of eight. Various methods of implementing this dynamic frequency-voltage scaling have been described in the conventional art.
A highly effective system for adjusting voltage to correspond with processing demands is commercially available on processors from Transmeta Corporation of Santa Clara, Calif. Embodiments of such systems are described in U.S. patent application Ser. No. 09/484,516, now U.S. Pat. No. 7,100,061, entitled Adaptive Power Control, to S. Halepete et al., filed Jan. 18, 2000, and assigned to the assignee of the present Application.
Halepete et al. disclose a processor's ability to dynamically adapt its voltage and clock frequency to correspond to the demands placed on the processor by software. Because dynamic power varies linearly with clock speed and by the square of voltage, adjusting both can produce cubic or higher order reductions in dynamic power consumption, whereas prior processors could adjust power only linearly (by only adjusting the frequency).
FIG. 1 illustrates an exemplary operating frequency versus supply voltage curve 110 for the operation of a microprocessor, according to the conventional art. Curve 110 indicates the required supply voltage Vdd to achieve a desired frequency of operation. For example, in order to operate at frequency 120, a supply voltage 160 is required.
Curve 110 may be established as a standard for a population of microprocessors, e.g., by collecting frequency versus voltage information for a number of microprocessor samples. By using a variety of well known statistical analysis methods, curve 110 may be established to achieve an optimal trade-off of performance and process yield. For example, curve 110 may be established such that 90% of all production exhibits better frequency-voltage performance than curve 110. Using curve 110, a set of frequency-voltage operating points may be established. For example, frequency 150 is paired with voltage 190, frequency 140 with voltage 180, frequency 130 with voltage 170 and frequency 120 with voltage 160. Such a set of frequency-voltage pairings (or points) may also be expressed in the form of a table, as illustrated in Table 1, below:
TABLE 1FrequencySupply Voltage150190140180130170120160
Such processors are configured to operate at a number of different frequency and voltage combinations, or points. Special power management software monitors the processor and dynamically switches between these operating points as runtime conditions change in order to advantageously minimize dynamic power consumption by the processor.
Unfortunately, in the prior art, such power management software has been limited to operate with a single set of frequency-voltage operating points. A set of frequency-voltage operating points is determined, for example, during qualification testing of a specific processor model for a specific manufacturing process, and used in the operation of every device of that processor model. Such a set of frequency-voltage operating points is determined based upon a worst case operation of a population of processor devices, determined, e.g., prior to general availability of the processor devices.
Numerous characteristics related to power consumption of a processor integrated circuit (“microprocessor”) are highly variable across a manufacturing process. For example, maximum operating frequency, threshold voltage and capacitance may each vary by 30% or more, from batch to batch and even within the same wafer. Leakage current is exponential in the threshold voltage and may vary by 500% from nominal. As an unfortunate consequence, such a set of frequency-voltage operating points is based upon the worst case operation of a population of processor devices, determined, e.g., during a qualification process, generally prior to general availability of the processor devices.
Many processors, typically a majority of a manufactured population, are able to operate at more desirable frequency-voltage operating points than the single standard set based upon worst case performance. For example, if the standard set specifies 600 MHz operation at 1.2 volts, many individual processor devices may be able to operate at 600 MHz at only 1.1 volts. Such better performing processors, however, are detrimentally set to operate at the standard frequency-voltage operating point, wasting power. Further, such parts will typically have a lower threshold voltage, and if forced to operate at a higher supply voltage will demonstrate an increased leakage current. Both effects consume excess power and cause an undesirably shorter battery life than is optimal for such a particular processor device.
In addition, during the commercial lifetime of a processor model, numerous refinements and improvements in its manufacturing processes are typically made. Some of these may improve the power characteristics of the processor population, for example, rendering the pre-existing standard set of frequency-voltage operating points less than optimal.
The conventional art has focused primarily on reducing the dynamic power consumption of microprocessors. Unfortunately, static power consumption in modern semiconductor processes, e.g., processes with a minimum feature size of about 0.13 microns and smaller, is no longer a negligible component of total power consumption. For such processes, static power may be one-half of total power consumption. Further, static power, as a percentage of total power, is tending to increase with successive generations of semiconductor process.
For example, maximum operating frequency is generally proportional to the quantity (1−Vt/dd), that is, one minus the threshold voltage divided by the supply voltage (for small process geometries). As process geometry shrinks, supply voltage (Vdd) typically also is decreased in order to avoid deleterious effects such as oxide breakdown. Consequently, threshold voltage should also be decreased in order to maintain or increase a desirable maximum operating frequency. Correspondingly, gate oxides are made thinner so that a gate can maintain control of the channel. A thinner gate oxide leads to an increased gate capacitance. Since “off” or leakage current of a CMOS device is generally proportional to gate capacitance, the trend to make gate oxides thinner tends to increase leakage current. Unfortunately, increasing leakage current deleteriously increases static power consumption. As an unfortunate result, the on-going decrease in semiconductor process size also leads to an ever-increasing share of total power consumption deriving from static power dissipation.
In addition, because leakage current is influenced by numerous aspects of device geometry and implant characteristics, static power may vary by as much as 500% above or below nominal levels. As performance in terms of power consumption is a critical attribute for a mobile processor, processor manufacturers typically test and certify that a part will meet a particular clock rate at a maximum power level, e.g., 1 GHz at 8.5 watts. When operating with a fixed set of frequency-voltage operating points, such a maximum power level must be achieved at a voltage specified by the set of frequency-voltage operating points.
If a particular processor device is unable to meet the maximum power limit at the standard frequency-voltage operating point, then it is rejected or placed into a higher power, and therefore less desirable category or “bin” at manufacturing test. Such a part represents a yield loss and a loss of potential revenue to the manufacturer. However, such a part may oftentimes be able to achieve both the required clock rate and power consumption specifications at a lower voltage.
Thus, while the systems and techniques of controlling frequency-voltage operating points in the prior art have brought about improvements in reduced power consumption of processors, the use of a standard set of operating points across a variable population of processors results in less than optimal power consumption and manufacturing yield losses that are highly undesirable.